1. Field
Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof.
2. Description of Related Art
In semiconductor memory devices, a chip size may affect the competitiveness of products. Thus, a vast amount of research has been conducted on reducing the chip size. Downscaling a circuit linewidth and providing an optimal circuit layout may be important to reduce the chip size.
In recent years, an increase in the integration density of semiconductor memory devices has led to not only power reduction and performance improvement but also a reduction in the fabrication cost of the semiconductor memory devices. Thus, semiconductor manufacturers are concentrating their efforts on increasing yield per wafer by reducing a cell size and a memory core area.
That is, as the integration degree and operating performance of semiconductor memory devices increase, areas occupied by memory cores may also increase. Therefore, efficiently reducing a memory core area to strengthen the cost competitiveness of semiconductor memory devices may be important.
FIG. 1A is a partial block diagram of a conventional semiconductor memory device 100.
Referring to FIG. 1A, the conventional semiconductor memory device 100 may include a plurality of memory cell array blocks 5-1 to 5-16, a plurality of pairs of local input/output data lines (LIO1, LIO1B) and (LIO2, LIO2B), a plurality of bit line sense amplifiers 10-1 to 10-4, a plurality of first prechargers (or precharge circuits) 60-1 to 60-4, a plurality of second prechargers (or precharge circuits) 70-1 to 70-4, and a plurality of local input/output sense amplifiers 80-1 to 80-4.
Referring to FIG. 1A, the pairs of local input/output data lines (LIO1, LIO1B) and (LIO2, LIO2B) may be connected to the bit line sense amplifiers 10-1 to 10-4, the first prechargers 60-1 to 60-4, the second prechargers 70-1 to 70-4, and the local input/output sense amplifiers 80-1 to 80-4. The bit line sense amplifiers 10-1 to 10-4, the first prechargers 60-1 to 60-4, the second prechargers 70-1 to 70-4, and the local input/output sense amplifiers 80-1 to 80-4 may be sufficiently arranged in a region among the memory cell array blocks 5-1 to 5-16.
FIG. 1B is a partial block diagram of another conventional semiconductor memory device 150. The conventional semiconductor memory device 150 may have a smaller number of memory cell array blocks than the conventional semiconductor memory device 100 shown in FIG. 1A.
Referring to FIG. 1B, the conventional semiconductor memory device 150 may include a reduced number of memory cell array blocks 55-1 to 55-8. The number of memory cell array blocks may be reduced in order to decrease a memory core area. A region among the memory cell array blocks 55-1 to 55-8 may be approximately one half or less than the region among the memory cell array blocks 5-1 to 5-16 of the semiconductor memory device 100 shown in FIG. 1A. In other words, the number of memory cell array blocks 55-1 to 55-8 of FIG. 1B and a length of the pairs of local input/output data lines (LIO1, LIO1B) and (LIO2, LIO2B) may be reduced by approximately half, as compared with the semiconductor memory device 100 in FIG. 1A. As a result, arranging the bit line sense amplifiers 10-1 to 10-4, the first prechargers 60-1 to 60-4, the second prechargers 70-1 to 70-4, and the local input/output sense amplifiers 80-1 to 80-4 of FIG. 1A in the reduced region of FIG. 1B may be difficult.
FIG. 2 is a partial block diagram of a conventional semiconductor memory device 200.
Referring to FIG. 2, the conventional semiconductor memory device 200 may include a plurality of bit line sense amplifiers 10-1 and 10-2, a control signal generator 30, a first precharge voltage generator 40, a second precharge voltage generator 50, a plurality of first prechargers 60-1 and 60-2, a plurality of second prechargers 70-1 and 70-2, and a plurality of local input/output sense amplifiers 80-1 and 80-2. The control signal generator 30 may generate a first precharge control signal C1 and a second precharge control signal P1
The first precharger 60-1 may be connected between the pair of local input/output data lines LIO1 and LIO1B. The first precharger 60-1 may include precharge transistors Q_N1 and Q_N2 and an equalization transistor Q_N3. The precharge transistors Q_N1 and Q_N2 and the equalization transistor Q_N3 may include a thin gate insulating layer.
In the first precharger 60-1, a drain of the precharge transistor Q_N1 may be connected to the local input/output data line LIO1 and a drain of the precharge transistor Q_N2 may be connected to the local input/output data bar line LIOB. A source of the precharge transistor Q_N1 may be connected to a source of the precharge transistor Q_N2 such that a first precharge voltage VINT may be commonly applied to the sources of the precharge transistors Q_N1 and Q_N2. Gates of the transistors Q_N1 to Q_N3 may be commonly connected and controlled in response to the first precharge control signal C1.
In the first precharger 60-1, a source of the equalization transistor Q_N3 may be connected to the local input/output data line LIO1 and a drain of the equalization transistor Q_N3 may be connected to the local input/output data bar line LIO1B.
The second precharger 70-1 may also be connected between the pair of local input/output data lines LIO1 and LIO1B. The second precharger 70-1 may include precharge transistors Q_K1 and Q_K2 and an equalization transistor Q_K3. The precharge transistors Q_K1 and Q_K2 and the equalization transistor Q_K3 may include a thick gate insulating layer. A drain of the precharge transistor Q_K1 may be connected to the local input/output data line LIO1 and a drain of the precharge transistor Q_K2 may be connected to the local input/output data bar line LIO1B. A source of the precharge transistor Q_K1 may be connected to a source of the precharge transistor Q_K2 such that a second precharge voltage VBL may be commonly applied to the sources of the precharge transistors Q_K1 and Q_K2.
In the second precharger 70-1, a source of the equalization transistor Q_K3 may be connected to the local input/output data line LIO1, and a drain of the equalization transistor Q_K3 may be connected to the local input/output data bar line LIO1B. Gates of the transistors Q_K1 to Q_K3 may be commonly connected and controlled in response to the second precharge control signal P1.
The second precharge voltage VBL may be an external voltage level. The first precharge voltage VINT may be an internal power supply voltage level. The second precharge voltage VBL may be approximately ½ of the internal power supply voltage level.
The details of the bit line sense amplifier 10-2, the first and second prechargers 60-2 and 70-2 and the local input/output sense amplifier 80-2 are similar to the bit line sense amplifier 10-1, the first and second prechargers 60-1 and 70-1 and the local input/output sense amplifier 80-1, and are omitted for the sake of brevity.
A conventional operation of the conventional semiconductor memory device 200 will now be described with reference to FIG. 2.
When a memory cell receives an enabled word line signal and outputs written/stored data to a pair of bit lines BL and BLB, the bit line sense amplifier 10-1 may receive charges stored in a capacitor of the memory cell through the pair of bit lines BL and BLB and may amplify a voltage corresponding to the charges.
The control signal generator 30 may receive external commands CMD and generate the first and second precharge control signals C1 and P1. The first and second precharge voltage generators 40 and 50 may receive an external power supply voltage VEXT and generate the first precharge voltage VINT and the second precharge voltage VBL, respectively.
The first precharger 60-1 may precharge data signals transmitted to the pair of local input/output data lines LIO1 and LIO1B to the first precharge voltage VINT in response to the first precharge control signal C1. For example, the precharge transistors Q_N1 and Q_N2 may be activated in response to the first precharge control signal C1 and may transmit the first precharge voltage VINT to the pair of local input/output data lines LIO1 and LIO1B. Also, the equalization transistor Q_N3 may be activated in response to the first precharge control signal C1 and may equalize the data signals transmitted to the pair of local input/output data lines LIO1 and LIO1B at the first precharge voltage VINT.
Thereafter, once precharge operation begins, the second precharger 70-1 may precharge the data signals transmitted to the pair of local input/output data lines LIO1 and LIO1B to the second precharge voltage VBL in response to the second precharge control signal P1.
For example, the precharge transistors Q_K1 and Q_K2 may be activated in response to the second precharge control signal P1 and may transmit the second precharge voltage VBL to the pair of local input/output data lines LIO1 and LIO1B. Also, the equalization transistor Q_K3 may be activated in response to the second precharge control signal P1 and may equalize the data signals transmitted to the pair of first local input/output data lines LIO1 and LIO1B at the second precharge voltage VBL.
The local input/output sense amplifier 80-1 may receive the equalized data signals from the pair of local input/output data lines LIO1 and LIO1B, may amplify voltage levels of the received signals, and may output the amplified signals to a pair of global data input/output data lines GIO1 and GIO1B.
FIGS. 3A through 3D illustrate conventional layouts of the plurality of first and second prechargers 60-1, 70-1, 60-2 and 70-2, respectively, of the conventional semiconductor memory devices 100 and 200 shown in FIGS. 1A and 2.
FIG. 3A illustrates a conventional layout of the first precharger 60-1 and the pair of local input/output data lines LIO1 and LIO1B shown in FIGS. 1A and 2.
Referring to FIG. 3A, the first precharger 60-1 may be interposed between a local input/output data line LIO1 and a local input/output data bar line LIO1B. An area interposed between the local input/output data line LIO1 and the local input/output data bar line LIO1B may include an active area, which is disposed at a lower level and divided into several sections. A first precharge control signal line C1 may be arranged on the active area. The local input/output data line LIO1, the local input/output data bar line LIO1B, and the first precharge voltage line VINT may be disposed at a higher level.
The active area may be electrically connected to the local input/output data line LIO1 by an input/output data line contact IO1C and electrically connected to the local input/output data bar line LIO1B by an input/output data bar line contact IOB1C. Also, the active area may be electrically connected to the first precharge voltage line VINT by a first precharge voltage data line contact VINTC.
Thus, the precharge transistor Q_N1 may be arranged between the local input/output data line contact IO1C and the local input/output data bar line contact IOB1C. The precharge transistor Q_N2 may be arranged between the local input/output data line contact IO1C and the first precharge voltage line contact VINTC. Also, the equalization transistor Q_N3 may be arranged between the local input/output data bar line contact IOB1C and the first precharge voltage line contact VINTC.
FIG. 3B illustrates a conventional layout of the second precharger 70-1 and the pair of local input/output data lines LIO1 and LIO1B shown in FIGS. 1A and 2.
Referring to FIG. 3B, the second precharger 70-1 may include an active area, which is disposed at the lower level and divided into several sections. A second precharge control signal line P1 may be arranged on the active area. A local input/output data line LIO1, a local input/output data bar line LIO1B, and a second precharge voltage line VBL may be disposed at a higher level.
Similarly, the active area may be electrically connected to the local input/output data line LIO1 by the input/output data line contact IO1C and electrically connected to the local input/output data bar line LIO1B by the input/output data bar line contact IOB1C. Also, the active area may be electrically connected to the second precharge voltage line VBL by a second precharge voltage line contact VBLC.
Thus, the precharge transistor Q_K1 may be arranged between the local input/output data line contact IO1C and the local input/output data bar line IOB1C. The precharge transistor Q_K2 may be arranged between the local input/output data line contact IO1C and the second precharge voltage line contact VBLC. Also, the equalization transistor Q_K3 may be arranged between the local input/output data bar line contact IOB1C and the second precharge voltage line contact VBLC.
FIGS. 3C and 3D illustrate a conventional layout of the first precharger 60-2, the second precharger 70-2, and the pair of local input/output data lines LIO2 and LIO2B shown in FIGS. 1A and 2. The prechargers 60-2 and 70-2 arranged between the local input/output data line LIO2 and local input/output data bar line LIO2B illustrated in FIGS. 3C and 3D are generally the same as the prechargers 60-1 and 70-1 except that the pair of local input/output data lines LIO1 and LIO1B are replaced by the pair of second local input/output data lines LIO2 and LIO2B.
Accordingly, in the conventional semiconductor memory devices as shown in FIGS. 3A-D, the first and second precharge control signal lines C1 and P1 connected to the pairs of local input/output data lines (LIO1, LIO1B) and (LIO2, LIO2B) may be separately arranged in different sections. Also, active areas in which the precharge transistors Q_N1, Q_N2, Q_K1, and Q_K2 of the first and second prechargers 60-1, 60-2, 70-1, and 70-2 are arranged may be separately arranged in different sections. Thus, increasing the integration density of conventional semiconductor memory devices may be difficult due to the conventional layout of the components.
Accordingly, if the number of memory cell array blocks is reduced as shown in FIG. 1B, arranging the bit line sense amplifiers 10-1 to 10-4, the first prechargers 60-1 to 60-4, the second prechargers 70-1 to 70-4, and the local input/output sense amplifiers 80-1 to 80-4 of FIG. 1A in the layout of FIG. 1B may be difficult.